1. Field of the Invention
The present invention is concerned with electron devices with ultra-short transit times, and more particularly with semiconductor devices which are hermetically sealed in a vacuum and in which charge carriers move through a vacuum.
2. Description of the Prior Art
The operation of semiconductor devices in a vacuum environment has been known in the prior art.
U.S. Pat. No. 3,105,166 (Choyke et al) provides a cold emissive cathode for emitting electrons into a vacuum. A PN junction is reverse biased by an electric field between the cathode and anode. The diode is enclosed in a vacuum tight container, and reverse bias of 7 to 20 volts is provided to the junction. A collecting potential of 135 volts is aplied to the anode.
U.S. Pat. No. 3,310,701 (Heimann) discloses a photo-cathode responsive to light radiation for emitting luminous energy electrons in an evacuated envelope. The electrons travel through the vacuum to the anode under the influence of operating potential applied to the cell. The photoemissive layer is P type and is adjacent an N type layer in the structure of FIG. 1.
U.S. Pat. No. 4,197,564 (Klimin et al) provides a photo-emitter coated with a layer reducing the electron work function of the substrate.
U.S. Pat. No. 4,163,949 (Shelton) teaches an apparatus comprising an emitting fiber for emitting electrons for collection by an anode or collector. Emission is responsive to application of a potential and may be further controlled by variation of applied potential to a conducting layer used to form a grid or control electrode. Electrons are emitted in a vacuum and the device combines features of a vacuum tube and a transistor.
U.S. Pat. No. 3,593,067 (Flynn) discloses an integrated diode array, having a plurality of grooves isolating the individual diodes, the array is biased so that the charge depletion layer of the PN junction extends beyond the grooves. Radiation is directed at one layer covering a single P layer for the entire structure. The grooves are formed at the bottom of the structure and electrons travel through the solid material.
U.S. Pat. No. 4,100,564 (Sasayama) discloses a semiconductor structure including a N+ layer below an N type substrate layer, the combination surmounted by a P type layer. The structure is provided with grooves.
U.S. Pat. No. 4,106,975 (Berkenblit) teaches a method for etching an aperature, with a particular crystallographic geometry, in single crystals which includes a step of anisotropically etching the structure. The resultant groove is depicted as being substantially vertical through three layers and has a "V" shaped cross-section through the substrate. One of the layers is a platinum-type while the other layers are both chromium-type.
U.S. Pat. No. 4,140,558 (Murphy et al) provides a multi-layer semiconductor device having a number of narrow grooves, having sidewalls in the (111) plane etched into the structure. The grooves are used for isolation of individual circuits.
U.S. Pat. No. 3,885,189 (Picker et al) discloses a semiconductor junction used as a target in a CRT. The semiconductor layer is rendered relatively highly conductive on the side of the target exposed to the light by overdoping the surface with the same conductivity type impurity as the remainder of the body. The opposite side of the layer has a junction formed therewith by a layer of dielectric material of substantially higher bulk resistance.
U.S. Pat. No. 2,776,367 (Lehovec) discloses an interaction between photons and conductors in a PN junction, providing a photon modulated, semiconductor current source.
A grooved structure, having a plurality of PNPN light activated switches, is shown in U.S. Pat. No. 3,344,278 (Yanai). Operation of the device, however, does not rely upon a vacuum in the regions between the several individual switches.
Although some of the above noted prior art does disclose electron emission into a vacuum, such references do not disclose or anticipate high speed semiconductor devices using charge carrier transport through a vacuum.